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Program

Tutorial
Sydney Hall (2F)
Tutorial 1
Oct. 12th | 13:00-14:00
Designing compact SoC PWM switched-inductor power supplies

Gabriel A. Rincón-Mora
Motorola Solutions Foundation Professor
School of Electrical and Computer Engineering
Georgia Institute of Technology, USA
Biography

Gabriel A. Rincón-Mora is Motorola Solutions Foundation Professor, Fellow of the National Academy of Inventors, Fellow of the IEEE, and Fellow of the Institution of Engineering and Technology. He was with Texas Instruments in 1994–2004 and has been with the Georgia Institute of Technology since 1999. He’s received the IEEE Charles A. Desoer Technical Achievement Award, Distinguished Faculty Achievement Award, IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award, IEEE Outstanding Educator Award, Charles E. Perry Visionary Award, Three-Year Patent Award, National Hispanic in Technology Award, Orgullo Hispano Award, Hispanic Heritage Award, State of California Commendation Certificate, and IEEE Service Award. His body of work includes 4 textbooks, 5 slide books, 3 literary books, 8 handbooks, 4 book chapters, 44 patents, over 200 articles, over 26 commercial power-chip products released to production, 25 educational videos, and over 170 keynote addresses, distinguished lectures, and research seminars.

Abstract

Switched-inductor power supplies are pervasive in electronics. This is because they deliver a large fraction of the power they draw from the input source with an output current or voltage that is largely independent of the load. Keeping the output current or voltage steady this way is ultimately the responsibility of the feedback controller. This
talk uses insight and intuition to show how SoC pulse-width-modulated (PWM) loops switch the inductor and offset the current or voltage they control. The presentation reviews the feedback response of switched inductors and discusses how PWM loops operate, control, and offset the current or voltage they regulate. The material covers current and voltage loops, current-mode voltage loops, load-dump response and compensation, and compact SoC contractions.

Tutorial 2
Oct. 12th | 14:00-15:00
Overcoming the Transimpedance Limit: On the Design of Low-Noise TIA

Dan Li
Professor
School of Microelectronics
Xi’an Jiaotong University, China
Biography

Dan Li received the B.E. and M.E. degrees from Northwestern Polytechnical University, Xi’an, in 2004 and 2007, respectively, and the Ph.D. degree from the University of Pavia, Pavia, Italy, in 2013. From 2007 to 2009, he worked at the Nvidia Shanghai R&D Center, where he focused on custom SRAM circuit design. From 2011 to 2014, he was with the Studio di Microelettronica, STMicroelectronics, Pavia, Italy, working on CMOS optical receivers for 100 GbE optical links and silicon photonics applications. He joined Xi’an Jiaotong University, Xi’an, in 2015, where he currently serves as a professor. His current research interests include high-speed optical interconnects, 3D sensing, and low-power mixed-signal circuits. He has served as Track Chair (Wireline) and TPC Member of IEEE ICTA, Publicity Chair of IEEE ICECS 2020, Sponsorship/Exhibition Chair of IEEE ICTA 2022, and Local Arrangement Chair of IEEE BioCAS 2024.

Abstract

With the mass deployment of optical links to meet the ever-increasing communication bandwidth demands from data communication and AI, there is a growing need for low-cost components. Furthermore, the advent of Co-Packaged Optics (CPO)—where electronics and photonics are integrated into a single package—will further drive improvements in bandwidth density and power efficiency. In this context, integrated solutions are not only desirable but often essential, leading to the adoption of silicon photonics and CMOS-based electronics, replacing the traditional dominance of III-V optics and SiGe electronics.
While CMOS is optimized for large-scale, digital-intensive functions, it has inherent weaknesses in high-speed analog performance. This tutorial addresses the design challenges in CMOS optical receiver (Rx) front-ends, with a particular focus on low noise. Noise is one of the most critical factors determining receiver performance and remains the most challenging aspect of Rx design. This is largely constrained by the relatively poor performance of CMOS transistors in terms of transconductance, gain, breakdown voltage, and linearity—limiting their use in broader scenarios such as long-reach and high-modulation applications.
To address this, the concept of “overcoming the transimpedance limit” is introduced as the underlying principle for low-noise receiver design. Under this methodology, two approaches are presented as toolkits for low-noise transimpedance amplifier (TIA) design: Type I (Breaking the Transimpedance Limit) and Type II (Exceeding the Transimpedance Limit). Design examples across various electronic and photonic technologies will be provided to guide the audience at both conceptual and practical levels. This tutorial helps researchers, students, and practitioners grasp the fundamentals of and gain insights into designing optical transceivers, silicon photonics systems, wireline communications, and high-speed electronics.

Tutorial 3
Oct. 12th | 15:00-16:00
Short-Length ECC Decoders: Design Challenges for Future URLLC Systems

Youngjoo Lee
Associate Professor
Electrical Engineering
Korea Advanced Institute of Science and Technology (KAIST), Korea
Biography

Youngjoo Lee received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2008, 2010, and 2014, respectively.

Since 2025, he has been with the School of Electrical Engineering at KAIST, where he is currently an Associate Professor. Prior to joining KAIST, he was with the Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, from 2014 to 2015, where he worked on reconfigurable SoC platforms for software-defined radio systems. He was an Assistant Professor in the Department of Electronic Engineering at Kwangwoon University, Seoul, South Korea, from 2015 to 2017. From 2017 to 2025, he served as a faculty member in the Department of Electrical Engineering at Pohang University of Science and Technology (POSTECH), Pohang, South Korea.

His current research interests include algorithm-hardware co-design for application-specific processors, energy-efficient machine learning accelerators, advanced error correction codes, and next-generation wireless systems.

More information is available at: https://sites.google.com/view/epiclab

Abstract

As 5G advances and 6G approaches, ultra reliable low latency communication (URLLC) is becoming increasingly important in next generation wireless systems. The growing presence of intelligent applications such as autonomous systems, real time control, and on device AI has led to a rapid increase in the demand for fast and reliable transmission of short data packets. This shift brings new and significant challenges to error correction coding, especially in terms of decoding performance, latency, throughput, and energy efficiency.

Short length ECC decoders, unlike those designed for longer codes, face unique design constraints due to limited redundancy and tighter timing requirements. Traditional approaches are often insufficient in these scenarios. In this tutorial, we will examine the key challenges in designing ECC decoders for URLLC applications using short codes. We will first explore how existing polar decoders, currently used in 5G systems, can be optimized for improved performance in short packet communication. In addition, we will discuss emerging ECC schemes that aim to replace the current 5G polar codes. We will highlight important considerations in decoder implementation for these new codes and compare their strengths and weaknesses against standard polar decoders

 
 
 

Capri Hall (2F)
Tutorial 4
Oct. 12th | 13:00-15:00
Advanced Techniques for High Efficiency Oversampling Data Converters from Discrete-Time to Continuous-Time: Fundamentals, Recent Trends, and Perspectives

Sai-Weng Sin, Terry
Professor
Faculty of Science and Technology
University of Macau, Macao, China
Biography

Sai-Weng Sin is currently a Professor with the Dept. of ECE, Faculty of Science and Technology, and the Deputy Director (Academic) of the Institute of Microelectronics, as well as the Deputy Director of State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau.
Dr. Sin is currently serving as the Associate Editor-in-Chief (Digital Communications) of the IEEE Transactions on Circuits and Systems II – Express Briefs, and the chair of the data converter subcommittee in the IEEE Custom Integrated Circuits Conference (CICC). He is/has been members of the Technical Program Committee of the IEEE Symposium of VLSI Circuits (VLSI), IEEE Asian Solid-State Circuits Conference (A-SSCC), International Symposium on Circuits and Systems (ISCAS), Int. Conference on Integrated Circuits, Technologies and Applications (ICTA), and Associate Editors of Journal of Semiconductor and IEEE Access, and Guest Editor of IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS). He is a Distinguished Lecturer of IEEE Solid-State Circuits Society from 2024 to 2025. He was the co-recipient of the 2011 ISSCC Silk Road Award and the 2011 State Science and Technology Progress Award (second-class), China.

Abstract

High efficiency oversampling data converters have become increasingly popular and significant in the various emerging applications, ranging from the data acquisition in IoT sensor nodes that demands an ultra-high resolution with very low power consumption to wideband wireless communications in medium/high resolution.
Part-I: Incremental ADCs (IADCs) play a vital role in modern applications, from high-end audio to IoT sensors. Significant advances in recent years have enhanced high-resolution IADC design, particularly in managing critical issues like thermal noise and DAC mismatches. This part provides a thorough examination of various design strategies within IADCs. It explores how weighting affects noise and mismatch performance, explains its role in algorithms, and presents cutting-edge architectures derived from academic research. Concrete design examples demonstrate these concepts in practice.
Part-II: Due to the resistive inputs and implicit anti-aliasing filtering, continuous-time (CT) delta-sigma ADCs (DS-ADCs) are favorable for wireless applications. The maximum clock frequency of CT DS-ADCs has increased significantly over the past decade. This trend results from advances in CMOS technologies and innovative ways to use this technology. This part covers the background and recent architectural and circuit innovations regarding CT DS-ADCs. Moreover, state-of-the-art examples will be presented as well as the future perspectives.

Liang Qi
Associate Professor
School of Integrated Circuits
Shanghai Jiao Tong University, China
Biography

Liang Qi (Senior Member, IEEE) received B.Sc. degree from Xidian University, China, in 2012 and Ph.D. degree from University of Macau, Macao, China, in 2019.
He currently works as an Associate Professor with the School of Integrated Circuits, Shanghai Jiao Tong University (SJTU). Before he joined SJTU, he worked with Shanghai Hisilicon, where he conducted the project of multi-band (2G-5G) RX ADC. He was a Visiting Scholar at Ulm University, Germany, during the Ph.D. studies. His research interests include high-performance data converters and analog mixed-signal integrated circuits.
Dr. Qi has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II – Express Briefs and the Integrated Circuits and Systems (ICAS) journal. He also is/has been a TPC Member for IEEE APCCAS, ICSICT, ICTA, and ASICON. He received Macao Scientific and Technology Research and Development for Postgraduate Award in 2016 and Outstanding Young Scholar Paper Award in IEEE ASICON 2021, respectively.

Tutorial 5
Oct. 12th | 15:00-16:00
SPAD-Based Solid-State LiDAR in CMOS: From Fundamentals to State-of-the-Art Integration

Seong-Jin Kim
Associate Professor
Department of System Semiconductor Engineering
Sogang University, Korea
Biography

Seong-Jin Kim received his B.S. degree in electrical engineering from the Pohang University of Science and Technology, Pohang, South Korea, in 2001, and M.S. and Ph.D. degrees in electrical engineering from KAIST, Daejeon, South Korea, in 2003 and 2008, respectively.
From 2008 to 2012, he was a Research Staff Member at the Samsung Advanced Institute of Technology, Yongin, South Korea, where he was involved in the development of CMOS imagers for real-time acquisition of 3-D images. From 2012 to 2015, he was with the Institute of Microelectronics, A*STAR, Singapore, where he was involved in the design of analog-mixed signal circuits for various sensing systems. From 2015 to 2024, he was an Associate Professor at the Ulsan National Institute of Science and Technology, Ulsan, South Korea. In 2024, he joined Sogang University, Seoul, South Korea, as an Associate Professor. He is a co-founder of SolidVue, a LiDAR startup company in South Korea. His current research interests include high-performance imaging devices, LiDAR systems, and biomedical interface circuits and systems.
Dr. Kim has served on the Technical Program Committee at the IEEE International Solid-State Circuits Conference (ISSCC) from 2019 to 2024 and was the Country Representative of South Korea for the ISSCC Far-East Region in 2021. He was a co-recipient of the IEEE ISSCC Silkroad Awards in 2020 and 2021.

Abstract

This tutorial will present a comprehensive overview of the enabling technologies behind single-photon avalanche diode (SPAD)-based solid-state CMOS LiDAR sensors that have emerged as a key component in autonomous vehicles and immersive mobile applications such as augmented and virtual realities (AR/VR). It will begin with an introduction to the fundamental principles of both direct and indirect time-of-flight (ToF) techniques. Subsequently, the tutorial will delve into the three core building blocks of a SPAD-based LiDAR system: (1) SPAD devices and analog front-end circuit to enable photon-level sensitivity; (2) time-to-digital converters (TDC) to translate photon arrival times into precise temporal measurements; and (3) histogram-based signal processing units to reconstruct depth information from stochastic photon detections. The session will finally explore recent advances in fully integrated on-chip histogramming TDC architectures, highlighting selected state-of-the-art implementations.