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Exynos On-device AIDr. Hyukjune Chung |
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Biography
2020 – Current: Samsung Electronics 2005 – 2020: Qualcomm Ph.D. University of Southern California, Department of Electrical Engineering, 2004 Abstract
In this talk, I will focus on on-device AI computing, and for this, I will present evolution of Exynos AI HW/SW solutions, challenges to support generative AI processing, and systematic approaches to overcome these challenges. |
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Silicon to Systems 2035: Re-Engineering Engineering for an AI-Driven WorldFrank Schirrmeister |
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Biography
Frank Schirrmeister is Executive Director, Strategic Programs, System Solutions in Synopsys’ Products & Markets Group. He leads strategic activities across system software and hardware assisted development for industries like automotive, data center and 5G/6G communications, as well as for horizontals like Artificial Intelligence / Machine Learning. Prior to Synopsys, Frank held various senior leadership positions at Arteris, Cadence Design Systems, Imperas, Chipvision, and SICAN Microelectronics, focusing on product marketing and management, solutions, strategic ecosystem partner initiatives, and customer engagement. He holds an MSEE from the Technical University of Berlin and actively participates in cross-industry initiatives as Engineering Program Chair at the ACM/IEEE Design Automation Conference. Abstract
By 2035, our world will be shaped by intelligent systems built upon semiconductor chips and systems of unimaginable complexity. These capabilities will redefine our day-to-day life from healthcare to transportation, but their creation demands a fundamental shift in how we design and engineer them. This presentation will present an outlook on the future of chip and system design, addressing the central question: How must we re-engineer engineering itself to meet the challenges of the next decade and beyond? The presentation will explore the forces shaping the silicon of 2035, from the dominance of software, semiconductor hardware complexity, to the intricacies chip architectures as the industry is pushing the boundaries of processing, memory and interconnect. A key focus will be the dual inflection point of Artificial Intelligence—both as the primary workload driving performance requirements for advanced computing from data centers to edges and as the essential tool for mastering development, verification, validation and implementation complexity of semiconductor devices. Extrapolating lessons from the past decade and insights from industry leaders, this presentation will identify the primary challenges facing our design flows, methodologies, and the engineering workforce. As an outlook for the semiconductor, systems and design automation space, this talk will discuss the necessary evolution of our tools and processes to enable the development of these advanced systems, providing a strategic perspective on how we can collectively build and distribute that future. |
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The Next-Generation AI Accelerator: Redefining Inference for a Sustainable AI FutureDr. Youngjin Cho |
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Biography
Youngjin Cho is Vice President of Hardware at FuriosaAI, where he leads the development of Abstract
As AI inference becomes ubiquitous infrastructure, the industry faces critical challenges in achieving sustainable and cost-effective computing. Current GPU-based solutions, not purpose-built for inference, suffer from poor energy efficiency that threatens AI scalability. This keynote presents TCP (Tensor Contraction Processor), a domain-specific architecture that elevates tensor contraction as the primitive operation. By introducing low-level einsum notation with explicit memory layout and scheduling, TCP enables unprecedented flexibility through software-defined topology and automated compilation, while achieving optimal performance. Our silicon implementation RNGD delivers 512 TFLOPS (FP8) at 150W TDP for air-cooled data centers, demonstrating 4.1× better first token latency and 2.7× improved throughput/watt on LLaMA-7B versus GPUs. This presentation will share our journey from concept to commercial deployment, examining how domain-specific design choices enable sustainable AI infrastructure |
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The Roadmap to the Future of Computing: Quantum-Centric SupercomputingDr. Hanhee Paik |
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Biography
Dr. Hanhee Paik is the Head of IBM Quantum Japan and a Senior Research Scientist at IBM Quantum. Her research career has been focused on understanding the coherence mechanisms of superconducting qubits and developing superconducting multi qubit architectures. Dr. Paik pioneered the novel design of a supercond ucting qubit that helped the industry push the quality of quantum computing performance, greatly impacting the quantum computing community. Today’s IBM Quantum systems’ coherence times benefit from Dr. Paik’s work. She played a pivotal role developing IBM Quantum’s 16 qubit processors. Over the last few years, she has turned her focus to IBM Quantum’s efforts to develop the global quantum ecosystem. Dr. Paik was elected an American Physical Society Fellow in 2021 for pioneering a novel superconducting qub it architecture that catalyzed the commercialization of superconducting quantum computing, and contributing to the advancement quantum computing research in the industry. Abstract
TBD |
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