Program

As broadband communication systems demand increasingly higher data rates, the role of High-speed DACs has become essential. Time-Interleaved DAC (TI-DAC) architectures are widely employed to achieve higher sampling speeds by operating multiple sub-DAC channels in parallel. However, employing two sub-channels in a Time-Interleaved structure increases array area and exacerbates power integrity challenges, which can further degrade dynamic performance typically measured by SFDR (Spurious-Free Dynamic Range). Moreover, the physical layout of each sub-DAC includes over 510-unit cells, and non-uniform routing paths between these cells can lead to dynamic mismatch in current summation, resulting in SFDR degradation. To mitigate these effects, the proposed design improves the SFDR from 40.97dBc to 51.25dBc.

Charge Pump circuit design presents significant challenges due to interrelated parameters, nonlinear component behavior, and complex performance trade-offs that traditionally require extensive iterations and simulation time. The proposed ML-Pump, a bidirectional predictive model, tackles these challenges by functioning in both forward and reverse directions. It predicts performance metrics (including output voltage, efficiency, and power) from design parameters (including width, length, capacitance, input voltage, load, etc.), and conversely, determines the optimal design parameters needed to achieve the desired performance characteristics. A single-stage cross-coupled charge pump implemented in 90nm CMOS technology was utilized for training and evaluating several machine learning models (Random Forest, MLP Regressor and Gradient Boosting) on a comprehensive dataset of approximately 65,000 samples generated from Cadence simulations. The MLP Regressor demonstrated superior performance with mean MSE of 2.09e-02 and MAE of 5.00e-02, outperforming Random Forest and Gradient Boosting algorithms. This bidirectional prediction capability enables designers to instantly evaluate performance impacts of parameter changes without time-consuming EDA tool simulations, significantly accelerating the design optimization process. This framework significantly speeds up the design process by enabling early prediction of performance metrics and design parameters, thereby improving efficiency and circuit performance.

Global Navigation Satellite Systems (GNSS) provide essential Position, Velocity, and Time (PVT) information using radio signals transmitted from satellites orbiting Earth. Accurate evaluation of GNSS signals and receiver performance requires realistic simulation environments, particularly for the Carrier-to-Noise Density Ratio (C/N₀), a critical indicator reflecting signal quality dependent on satellite elevation angles. This paper presents the development of a GNSS testbed specifically designed to simulate and estimate C/N₀ values, focusing on GPS L1C/A signals. The proposed testbed includes a satellite simulator that controls signal power accurately according to satellite elevation angles, and a GNSS receiver that utilizes the Narrowband-Wideband Power Ratio (NWPR) method for precise C/N₀ estimation. Experimental results demonstrate that the implemented testbed accurately generates realistic GNSS signals, maintaining an average accuracy of 0.38 dB-Hz for elevation angles above 45°, and 1.52 dB-Hz for elevation angles below 45°. It is clear that simulation accuracy improves as elevation angle increases, confirming the effectiveness of the testbed for reliable GNSS signal analysis and receiver performance evaluation under various operational scenarios.

This paper presents intelligent multi-energy harvesting with GaN devices for smart home applications. In a smart home, such a system can provide energy to various small devices, like sensors, using rf energy and solar energy from natural sunlight and artificial light sources like fluorescent lamps. To supply solar energy to indoor sensors, it can be converted to rf energy and transmitted over long distances. GaN FETs are proposed to maximize efficiency in this conversion process, utilizing the ST-ZCD (Self-Tuned Zero Current Detection) method and an adaptive dead time circuit to ensure stable operation. These techniques achieve a peak efficiency of 97.64%, with a 3% efficiency. The high power solar energy harvesting IC with GaNFET, developed using a 180 nm BCD process, is integrated with GaN FETs on a board. The area is 5 mm × 2.5 mm. Experimental results confirm its ability to reliably deliver 5 V of power over 5 meters to the high efficiency multi energy harvesting IC, demonstrating efficient solar energy harvesting and RF energy transmission. The high efficiency multi energy harvesting IC harvests energy from external solar energy converted to rf energy, ambient rf energy, and artificial light sources within the home. It features an RF-DC converter and a system for harvesting indoor light energy, developed using a 130 nm BCD process. The area is 2.01 mm × 2.01 mm. To enable self-boosting at low voltages, the IC employs an adaptive body bias controller to lower the threshold voltage during the cold start phase, allowing self-boosting from as low as 300 mV. The proposed IC optimizes ON time based on input power and uses a self-clock ZCD to achieve a maximum efficiency of 91.27%. The RF-DC converter uses Schottky diodes to minimize the threshold voltage and MOSFETs to compensate for reverse leakage current, achieving an efficiency of 62%.

his study presents an ultra-low-power surveillance system that fuses Dynamic Vision Sensors (DVS) [5], [11], [14], [15] and CMOS Image Sensors (CIS) for real-time object detection. DVS offer ultra-low latency and high dynamic range with minimal energy, making them ideal for efficient visual processing [7], [9]. However, conventional always-on systems waste energy on redundant deep neural network (DNN) inference. To address this, we propose a DVS-based Region-of-Interest (ROI) detection algorithm that identifies motion-triggered regions and selectively activates a neural processing unit (NPU) only when meaningful activity occurs. The algorithm models DVS event distributions using a probabilistic framework and extracts ROI using Kadane’s maximum subarray algorithm, enabling linear-time inference triggering. Implemented on a dual-FPGA platform with a YOLOv3-Tiny NPU, the system achieves a 31.5% reduction in energy consumption over a 24-hour deployment while maintaining real-time performance with an 18ms inference latency.